1. Field of the Invention
The present invention relates to network communication devices, such as ATM (Asynchronous Transfer Mode) switches, which discard invalid packets.
2. Description of the Background Art
The network communication devices on a network like the Ethernet switch and the ATM switch handle masses of data (hereinafter referred to as packets) as units. Such network communication devices switch packets through hardware to realize high throughput. The ATM switch is the hardware for switching lines. It is determined by an international recommendation that the ATM switches should handle fixed-length (53-byte) packets. Among the packets, fixed-length packets are called "cells."
FIG. 22 is a diagram showing the concept of an example of a conventional ATM switch 100a. Input lines IN#1-4 and output lines OUT#1-4 are connected to the ATM switch 100a. An input portion 11 is connected to the input lines IN#1-4. An output portion 13 is connected to the output lines OUT#1-4. A line interface 11a, a destination analyzing portion 11b and an in-device interface 11c are provided for each of the input lines IN#1-4. A line interface 13a, a destination adding portion 13b and an in-device interface 13c are provided for each of the output lines OUT#1-4. The input portion 11 receives cells provided with destinations from the input lines IN#1-4. In the input portion 11, data in the cells (cell data) are transferred to the switch portion 12 through the line interface 11a, the destination analyzing portion 11b for analyzing the destinations and adding in-device management information to the cell data, and the in-device interface 11c.
Next, the switch portion 12 outputs the cell data to the in-device interfaces 13c corresponding to the destinations. In the output portion 13, the cells are transferred to the target lines through the in-device interface 13c, the destination adding portion 13b for removing the in-device management information added to the cell data and adding destinations to the cells, and the line interface 13a. Thus, the switch portion 12 transfers the cells received from the plurality of input lines to the output lines corresponding to the destinations.
When a plurality of cells directed to a certain output line are received from a plurality of input lines at the same time, the cell data collide (congestion). To avoid the congestion, first, the switch portion 12 once stores the plurality of cell data received from the plurality of input lines into the built-in buffer memory BM. The plurality of cell data directed to a certain output line stored in the buffer memory BM are placed in the wait state until that output line is freed. When the output line becomes free, the switch portion 12 outputs the plurality of cell data directed to that output line to the output portion 13.
The ATM switches containing such a buffer memory BM include those called "shared-buffer ATM switches." The shared-buffer ATM switches include that described in the collection of preparatory manuscripts, Masahiko Ishiwaki et al., "Efficient Self-timed Queue Architecture for a shared-buffering ATM Switch", Institute of Electronics, Information and Communication Engineers of Japan, Integrated Circuit Study Group, ICD94-67, June 1994.
A flow of a plurality of cells (a data stream) may become invalid. This is caused by a trouble on the network or in a terminal connected to the network, for example. Such a trouble is caused when a trouble, e.g., a data error, occurs, or when a request from a source party for connecting the line (hereinafter referred to as "a call") is unexpectedly disconnected, or when a data stream with low priority is interrupted due to congestion of cells on the network, for example.
The capability of managing the cell data in the conventional buffer memory BM is limited. The cell data are, mainly, managed only with the destinations. For example, this management cannot identify cell data belonging to an invalidated data stream. Accordingly, the conventional ATM switch 100a cannot discard invalid cells in the switch portion 12, but the input portion 11 and the output portion 13 discard the invalid cells. For example, suppose that discarding information for informing that cells belonging to a particular data stream are discarded was issued outside of the ATM switch 100a and then the ATM switch received the discarding information. Then the input portion 11 of the ATM switch 100a discards the cells corresponding to the discarding information among the received cells, or the output portion 13 of the ATM switch 100a discards the cells corresponding to the discarding information.
The ATM switch 100a requires high speed performance. Particularly, when a data stream with low priority is interrupted due to congestion of cells on the network, it is preferable to immediately discard the invalid cells. If the cells are not discarded at once, the congestion cannot be avoided.
In the conventional ATM switch 100a, however, the switch portion 12 does not discard invalid cells. Accordingly, the invalid cells cannot be discarded while they exist in the buffer memory BM. After the cell discarding information has been received, the invalid cells are discarded when the corresponding output line has become free and the switch portion 12 has outputted the invalid cells directed to that output line into the output portion 13. Thus, the conventional ATM switch 100a has the problem that even if invalid cells are accumulated in the buffer memory BM, they cannot be discarded at once.